The LVS (Layout vs. Schematic) module allows a chip designer to automatically compare netlists from manual or auto-routed layout against the schematic representation of that layout. LVS acts as a powerful tool in finding differences between two netlists, missing nodes, missing devices, shorts, broken nets, swiveled inputs and parametric differences between devices. Users can define non-standard devices in Spice, comparing resistors, inductors and capacitors either as polarized or non-polarized devices, and reducing parallel and serial devices, including recalculating their parameters. Since LVS accepts Spice format netlist files, a designer can output a schematic netlist from any schematic capture package supporting Spice.
Phanesh Janapareddi
Sales Engineer Tanner Research, Inc. 180 N. Vinedo Avenue Pasadena, CA 91107 USA 818-792-3000 fax:818-792-0300 sales@tanner.com