The Standard Cell Place and Route (SPR(tm)) allows users to generate a chip layout automatically from a netlist specification. This feature is composed of several modules: the SPR Block Generator, the Padframe Generator, and the Pad Router.
The SPR Block Generator placement optimizer based on the simulated annealing algorithm analyzes the design and decides how best to order the standard cells within the rows to produce the smallest layout.
The Core Block channel router is gridless and can be configured for a wide array of design rules. The router is capable of routing custom designed cells of Tanner Research's SCMOSLib cells, a MOSIS and Orbit Foresight compatible digital logic library.
The Padframe Generator and Pad Router do final pad assembly and pad-to-core river routing for push button assembly of digital netlists.
Phanesh Janapareddi
Sales Engineer Tanner Research, Inc. 180 N. Vinedo Avenue Pasadena, CA 91107 USA 818-792-3000 fax:818-792-0300 sales@tanner.com